1. Field of the Invention
The present invention generally relates to data processing and, in particular, to a system and method for efficiently providing predicate data that defines whether instructions processed by a processor pipeline should be executed by the pipeline.
2. Related Art
To improve performance of conventional computer systems, superscalar processors capable of pipeline processing have been developed. Such processors typically utilize a plurality of pipelines to process and execute instructions of a computer program. Each of the pipelines is capable of simultaneously processing a plurality of instructions. Therefore, such superscalar processors have the capability of quickly processing and executing a relatively large number of instructions.
It is well known that each instruction of a computer program is not necessarily executed during each run of the computer program. In this regard, many instructions are executed only if certain conditions are true. However, as the program runs, many of the instructions that should not be executed are input into the pipelines and processed by the pipelines. For example, consider a situation in which execution of a program should branch to one of two portions of the program based on the results of the execution of a compare instruction. In such a situation, it is generally desirable to input instructions from both portions of the program into the pipelines, which begin processing the instructions. However, only the instructions associated with one of the portions, depending on the execution results of the compare instruction, should be executed by the pipelines. The instructions in the other portion should pass through the pipelines without execution.
To enable such selective execution of instructions, each instruction is associated with a predicate register containing a predicate value that indicates whether or not the instruction is enabled. Although the predicate value can have various lengths, the predicate value is usually one bit of information. If asserted, the predicate value indicates that instructions associated with the predicate register are presently enabled and, therefore, should be executed. If deasserted, the predicate value indicates that instructions associated with the predicate register are presently disabled and, therefore, should not be executed.
In the example described hereinbefore, once the aforementioned compare instruction is executed and it is, therefore, known which portion of the program should execute, the predicate values contained in the registers associated with the instructions in the portion of the program that should execute are asserted, and the predicate values contained in the registers associated with the instructions in the portion of the program that should not execute are deasserted.
Furthermore, during the processing of the instructions in both portions of the program, the predicate values contained in the registers associated with the instructions are analyzed to determine whether each of the instructions is enabled. If the predicate data indicates that an instruction is enabled (i.e., the value in the predicate register associated with the instruction is asserted), then the instruction is executed by the pipeline processing the instruction. However, if the predicate data indicates that the instruction is disabled (i.e., the value in the predicate register associated with the instruction is deasserted), then the instruction is not executed by the pipeline processing the instruction. Accordingly, by maintaining and analyzing predicate data, the instructions in one of the aforementioned portions of the program can be executed by the pipelines, while the instructions in the other portion can pass through the pipelines without execution.
While the instructions are being processed by the pipelines, the predicate data can also be used to resolve data hazards. For example, it is well known that when an instruction is dependent on data that is not yet available, the instruction should be stalled before execution to prevent data dependency errors. Once the necessary data becomes available, the stall can be removed and the instruction can then be allowed to execute.
Although stalling prevents errors, the stalling of instructions increases the amount of time required to process the instructions. To minimize the adverse effects of stalls, the predicate value contained in a predicate register associated with an instruction that should otherwise be stalled can be analyzed to determine whether or not the instruction is enabled. If the instruction is disabled, then the instruction does not need to be stalled, since the instruction will not be executed and, therefore, will not cause an error. As a result, the predicate data can be used to prevent or remove unnecessary stalls and, therefore, to increase the performance of a processor.
The predicate registers are usually maintained in a register file that includes write and read ports to enable predicate data to be written to and read from the appropriate predicate register. The register file serves as a central location for storage of all of the predicate values utilized by the processing system. Therefore, when the predicate status of any instruction is needed by a portion of any of the pipelines, the predicate value contained in the predicate register associated with the instruction can be read from the register file. However, the write and read ports of the register file are relatively expensive in terms of area, wires, and often processor speed, and it is, therefore, desirable to minimize the number of write and read ports needed to write to and read from the register file.
Furthermore, the predicate value contained in a predicate register associated with an instruction of a program can be changed during execution of the program, as it becomes known which instructions should and should not execute as the program runs. To minimize delays in the pipelines, it is desirable for the circuitry of the pipelines to quickly receive any updates to the predicate data. However, writing and reading predicate values into and out of the register file utilizes a relatively significant amount of time (on the order of one or more clock cycles), thereby increasing the delay in notifying the circuitry of a change in the predicate data.
Thus, a heretofore unaddressed need exists in the industry for providing a system and method of efficiently providing predicate data to indicate whether instructions being processed by a processor should be executed.
The present invention overcomes the inadequacies and deficiencies of the prior art as discussed hereinbefore. The present invention generally relates to a system and method for efficiently providing predicate data that defines whether or not instructions processed by a processor pipeline should be executed by the pipeline.
In architecture, the system of the present invention utilizes a register, a pipeline, and predicate circuitry. The pipeline includes a first stage and a second stage for processing instructions of a computer program. The predicate circuitry is configured to read a first predicate value from the register and to receive a second predicate value. The predicate circuitry may transmit the first predicate value read from the register to the first stage and then select between the first predicate value and the second predicate value. The predicate value selected by the predicate circuitry is transmitted to the second stage.
If the instruction in the second stage is stalled, then the predicate value transmitted to the second stage is continuously selected and transmitted to the second stage for the duration of the stall, unless a new predicate value indicative of the predicate status of the instruction is received. If such a new predicate value is received, the new predicate value is selected and transmitted to the second stage instead.
The present invention can also be viewed as providing a method for processing instructions of a computer program. The method can be broadly conceptualized by the following steps: providing a pipeline having a first stage and a second stage; producing a predicate value; writing the predicate value to a register; receiving an instruction; receiving a control signal; reading the predicate value from the register based on a register identifier included in the instruction; transmitting the predicate value read in the reading step to the first stage of the pipeline; processing the instruction via the first stage of the pipeline based on the predicate value transmitted to the first stage; receiving a new predicate value; selecting, based on the control signal, between the new predicate value and the predicate value read in the reading step; transmitting the predicate value selected in the selecting step to the second stage of the pipeline; and processing the instruction via the second stage based on the predicate value selected in the selecting step.
Other features and advantages of the present invention will become apparent to one skilled in the art upon examination of the following detailed description, when read in conjunction with the accompanying drawings. It is intended that all such features and advantages be included herein within the scope of the present invention and protected by the claims.